1. Field of the Invention
The present invention relates to a semiconductor memory device with an on-die termination (ODT) circuit, and more particularly, to a semiconductor memory device and method capable of testing an on/off state of an on-die termination (ODT) circuit during a data read mode.
2. Description of the Related Art
A termination resistor that terminates a bus is generally used to provide impedance matching in systems that exchange signals. The termination resistor increases the integrity of a received signal by suppressing the reflection of the signal.
The termination resistor may be located outside or inside a semiconductor memory device. A termination resistor located in a semiconductor memory device is referred to as an on-die termination (ODT) resistor. Also, a circuit that includes and controls the ODT resistor is referred to as an ODT circuit.
FIG. 1 is a block diagram of a conventional semiconductor memory device 100 with an ODT circuit 130. Referring to FIG. 1, the conventional semiconductor memory device 100 includes the ODT circuit 130, an ODT pad 180, and an input/output (I/O) pad 190.
The ODT circuit 130 includes first and second ODT resistors R1 and R2 and first and second switches S1 and S2. When the first switch S1 is on, i.e., closed, the first ODT resistor R1 is connected to an ODT voltage source VDDQ. When the second switch S2 is on, the second ODT resistor R2 is connected to a ground voltage source VSSQ. The first and second switches S1 and S2 are turned on/off in response to an external control signal received via the ODT pad 180.
While the ODT circuit 130 is on, if data is read from the conventional semiconductor memory device 100, the accuracy of the read data is not guaranteed. Thus, the ODT circuit 130 must be turned off while a data read operation is performed. Also, in order to determine accuracy of the read data, it is important to determine whether the ODT circuit 130 is off during the data read operation.
However, the conventional semiconductor memory device 100 can recognize only the resistance values of the first and second ODT resistors R1 and R2 when a data read operation is not being performed. Accordingly, the conventional semiconductor memory device 100 is not capable of determining whether the ODT circuit 130 is on or off during the data read operation.